Methods of fabricating gallium nitride semiconductor layers by lateral growth from sidewalls into trenches, and gallium nitride semiconductor structures fabricated thereby

ABSTRACT

A sidewall of an underlying gallium nitride layer is laterally grown into a trench in the underlying gallium nitride layer, to thereby form a lateral gallium nitride semiconductor layer. Microelectronic devices may then be formed in the lateral gallium nitride layer. Dislocation defects do not significantly propagate laterally from the sidewall into the trench in the underlying gallium nitride layer, so that the lateral gallium nitride semiconductor layer is relatively defect free. Moreover, the sidewall growth may be accomplished without the need to mask portions of the underlying gallium nitride layer during growth of the lateral gallium nitride layer. The defect density of the lateral gallium nitride semiconductor layer may be further decreased by growing a second gallium nitride semiconductor layer from the lateral gallium nitride layer. In one embodiment, the lateral gallium nitride layer is masked with a mask that includes an array of openings therein. The lateral gallium nitride layer is then grown through the array of openings and onto the mask, to thereby form an overgrown gallium nitride semiconductor layer. In another embodiment, the lateral gallium nitride layer is grown vertically. A plurality of second sidewalls are formed in the vertically grown gallium nitride layer to define a plurality of second trenches. The plurality of second sidewalls of the vertically grown gallium nitride layer are then laterally grown into the plurality of second trenches, to thereby form a second lateral gallium nitride layer. Microelectronic devices are then formed in the gallium nitride semiconductor layer.

CROSS-REFERENCE TO PROVISIONAL APPLICATION

[0001] This application claims the benefit of Provisional ApplicationSerial No. 60/088,761, filed Jun. 10, 1998, entitled “Methods ofFabricating Gallium Nitride Semiconductor Layers by Lateral Growth FromSidewalls Into Trenches, and Gallium Nitride Semiconductor StructuresFabricated Thereby”.

FEDERALLY SPONSORED RESEARCH

[0002] This invention was made with Government support under Office ofNaval Research Contract No. N00014-96-1-0765. The Government may havecertain rights to this invention.

FIELD OF THE INVENTION

[0003] This invention relates to microelectronic devices and fabricationmethods, and more particularly to gallium nitride semiconductor devicesand fabrication methods therefor.

BACKGROUND OF THE INVENTION

[0004] Gallium nitride is being widely investigated for microelectronicdevices including but not limited to transistors, field emitters andoptoelectronic devices. It will be understood that, as used herein,gallium nitride also includes alloys of gallium nitride such as aluminumgallium nitride, indium gallium nitride and aluminum indium galliumnitride.

[0005] A major problem in fabricating gallium nitride-basedmicroelectronic devices is the fabrication of gallium nitridesemiconductor layers having low defect densities. It is known that onecontributor to defect density is the substrate on which the galliumnitride layer is grown. Accordingly, although gallium nitride layershave been grown on sapphire substrates, it is known to reduce defectdensity by growing gallium nitride layers on aluminum nitride bufferlayers which are themselves formed on silicon carbide substrates.Notwithstanding these advances, continued reduction in defect density isdesirable.

[0006] It is also known to fabricate gallium nitride structures throughopenings in a mask. For example, in fabricating field emitter arrays, itis known to selectively grow gallium nitride on stripe or circularpatterned substrates. See, for example, the publications by Nam et al.entitled “Selective Growth of GaN and Al _(0.2) Ga _(0.8) N onGaN/AlN/6H-SiC(0001) Multilayer Substrates Via Organometallic VaporPhase Epitaxy”, Proceedings of the Materials Research Society, December1996, and “Growth of GaN and Al ₀ ₂ Ga _(0.8) N on Patterened Substratesvia Organometallic Vapor Phase Epitaxy”, Japanese Journal of AppliedPhysics., Vol. 36, Part 2, No. 5A, May 1997, pp. L532-L535. As disclosedin these publications, undesired ridge growth or lateral overgrowth mayoccur under certain conditions.

SUMMARY OF THE INVENTION

[0007] It is therefore an object of the present invention to provideimproved methods of fabricating gallium nitride semiconductor layers,and improved gallium nitride layers so fabricated.

[0008] It is another object of the invention to provide methods offabricating gallium nitride semiconductor layers that can have lowdefect densities, and gallium nitride semiconductor layers sofabricated.

[0009] These and other objects are provided, according to the presentinvention by laterally growing a sidewall of an underlying galliumnitride layer into a trench in the underlying gallium nitride layer, tothereby form a lateral gallium nitride layer. Microelectronic devicesmay then be formed in the lateral gallium nitride layer.

[0010] It has been found, according to the present invention, thatdislocation defects do not significantly propagate laterally from thesidewall into the trench in the underlying gallium nitride layer, sothat the lateral gallium nitride semiconductor layer is relativelydefect free. The sidewall growth may be accomplished without the need tomask portions of the underlying gallium nitride layer during growth ofthe lateral gallium nitride layer.

[0011] According to another aspect of the present invention, a pair ofsidewalls of the underlying gallium nitride layer are laterally growninto a trench in the underlying gallium nitride layer between the pairof sidewalls until the grown sidewalls coalesce in the trench. Thelateral gallium nitride semiconductor layer may be laterally grown usingmetalorganic vapor phase epitaxy (MOVPE). For example, the lateralgallium nitride layer may be laterally grown using triethylgallium (TEG)and ammonia (NH₃) precursors at 1000-1100° C. and 45 Torr. Preferably,TEG at 13-39 μmol/min and NH₃ at 1500 sccm are used in combination with3000 sccm H₂ diluent. Most preferably, TEG at 26 μmol/min, NH₃ at 1500sccm and H₂ at 3000 sccm at a temperature of 1100° C. and 45 Torr areused. The underlying gallium nitride layer preferably is formed on asubstrate such as 6H—SiC(0001), which itself includes a buffer layersuch as aluminum nitride thereon. Other substrates such as sapphire, andother buffer layers such as low temperature gallium nitride, may beused. Multiple substrate layers and buffer layers also may be used.

[0012] The underlying gallium nitride layer including the sidewall maybe formed by forming the trench in the underlying gallium nitride layer,such that the trench includes the sidewall. Alternatively, the sidewallmay be formed by forming a post on the underlying gallium nitride layer,the post including the sidewall and defining the trench. A series ofalternating trenches and posts is preferably formed to form a pluralityof sidewalls. Trenches and/or posts may be formed by selective etching,selective epitaxial growth, combinations of etching and growth, or othertechniques. The trenches may extend into the buffer layer and into thesubstrate.

[0013] The sidewall of the underlying gallium nitride layer is laterallygrown into the trench, to thereby form the lateral gallium nitride layerof lower defect density than the defect density of the underlyinggallium nitride layer. Some vertical growth may also occur. Thelaterally grown gallium nitride layer is vertically grown whilepropagating the lower defect density. Vertical growth may also takeplace simultaneous with the lateral growth.

[0014] The defect density of the overgrown gallium nitride semiconductorlayer may be further decreased by growing a second gallium nitridesemiconductor layer from the lateral gallium nitride layer. In oneembodiment, the lateral gallium nitride layer is masked with a mask thatincludes an array of openings therein. The lateral gallium nitride layeris grown through the array of openings and onto the mask, to therebyform an overgrown gallium nitride semiconductor layer. In anotherembodiment, the lateral gallium nitride layer is grown vertically. Aplurality of second sidewalls are formed in the vertically grown lateralgalliun nitride layer to define a plurality of second trenches. Theplurality of second sidewalls of the vertically grown lateral galliumnitride layer are then laterally grown into the plurality of secondtrenches, to thereby form a second lateral gallium nitride layer.Microelectronic devices are then formed in the gallium nitridesemiconductor layer. The plurality of sidewalls of the underlyinggallium nitride layer may be grown using metalorganic vapor phaseepitaxy as was described above. The second sidewalls may be grown byetching and/or selective epitaxial growth of trenches and/or posts, aswas described above.

[0015] Gallium nitride semiconductor structures according to theinvention comprise an underlying gallium nitride layer including atrench having a sidewall, and a lateral gallium nitride layer thatextends from the sidewall of the underlying gallium nitride layer intothe trench. A vertical gallium nitride layer extends from the lateralgallium nitride layer. A plurality of microelectronic devices areincluded in the vertical gallium nitride layer. A series of alternatingtrenches and posts may be provided to define a plurality of sidewalls.The underlying gallium nitride layer includes a predetermined defectdensity, and the lateral gallium nitride layer is of lower defectdensity than the predetermined defect density.

[0016] Other embodiments of gallium nitride semiconductor structuresaccording to the invention comprise a mask including an array ofopenings therein on the lateral gallium nitride layer and a verticalgallium nitride layer that extends from the lateral gallium nitridelayer through the openings and onto the mask. Alternatively, a verticalgallium nitride layer extends from the lateral gallium nitride layer andincludes a plurality of second sidewalls therein. A second lateralgallium nitride layer extends from the plurality of second sidewalls.Microelectronic devices are included in the second lateral galliumnitride layer. Accordingly, low defect density gallium nitridesemiconductor layers may be produced, to thereby allow the production ofhigh performance microelectronic devices.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] FIGS. 1-5 are cross-sectional views of first embodiments ofgallium nitride semiconductor structures during intermediate fabricationsteps according to the present invention.

[0018] FIGS. 6-10 are cross-sectional views of second embodiments ofgallium nitride semiconductor structures during intermediate fabricationsteps according to the present invention.

[0019] FIGS. 11-15 are cross-sectional views of third embodiments ofgallium nitride semiconductor structures during intermediate fabricationsteps according to the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0020] The present invention now will be described more fullyhereinafter with reference to the accompanying drawings, in whichpreferred embodiments of the invention are shown. This invention may,however, be embodied in many different forms and should not be construedas limited to the embodiments set forth herein; rather, theseembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the scope of the invention to thoseskilled in the art. In the drawings, the thickness of layers and regionsare exaggerated for clarity. Like numbers refer to like elementsthroughout. It will be understood that when an element such as a layer,region or substrate is referred to as being “on” or “onto” anotherelement, it can be directly on the other element or intervening elementsmay also be present. Moreover, each embodiment described and illustratedherein includes its complementary conductivity type embodiment as well.

[0021] Referring now to FIGS. 1-5, methods of fabricating galliumnitride semiconductor structures according to a first embodiment of thepresent invention will now be described. As shown in FIG. 1, anunderlying gallium nitride layer 104 is grown on a substrate 102. Thesubstrate 102 may include a 6H—SiC(0001) substrate 102 a and an aluminumnitride buffer layer 102 b. The crystallographic designation conventionsused herein are well known to those having skill in the art, and neednot be described further. The gallium nitride layer 104 may be between1.0 and 2.0 μm thick, and may be grown at 1000° C. on a high temperature(1100° C.) aluminum nitride buffer layer 102 b that was deposited on the6H—SiC substrate 102 a in a cold wall vertical and inductively heatedmetalorganic vapor phase epitaxy system using triethylgallium at 26μmol/min, ammonia at 1500 sccm and 3000 sccm hydrogen diluent.Additional details of this growth technique may be found in apublication by T. W. Weeks et al. entitled “GaN Thin Films Deposited ViaOrganometallic Vapor Phase Epitaxy on α(6H)—SiC(0001) UsingHigh-Temperature Monocrystalline AlN Buffer Layers”, Applied PhysicsLetters, Vol. 67, No. 3, Jul. 17, 1995, pp. 401-403, the disclosure ofwhich is hereby incorporated herein by reference. Other substrates, withor without buffer layers, may be used.

[0022] Still referring to FIG. 1, the underlying gallium nitride layer104 includes a plurality of sidewalls 105 therein. It will be understoodby those having skill in the art that the sidewalls 105 may be thoughtof as being defined by a plurality of spaced apart posts 106, that alsomay be referred to as “mesas”, “pedestals”or “columns”.

[0023] The sidewalls 105 may also be thought of as being defined by aplurality of trenches 107, also referred to as “wells” in the underlyinggallium nitride layer 104. The sidewalls 105 may also be thought of asbeing defined by a series of alternating trenches 107 and posts 106. Itwill be understood that the posts 106 and the trenches 107 that definethe sidewalls 105 may be fabricated by selective etching and/orselective epitaxial growth and/or other conventional techniques.Moreover, it will also be understood that the sidewalls need not beorthogonal to the substrate 102, but rather may be oblique thereto.Finally, it will also be understood that although the sidewalls 105 areshown in cross-section in FIG. 1, the posts 106 and trenches 107 maydefine elongated regions that are straight, V-shaped or have othershapes. As shown in FIG. 1, the trenches 107 may extend into the bufferlayer 102 b and into the substrate 102 a, so that subsequent galliumnitride growth occurs preferentially on the sidewalls 105 rather than onthe trench floors. In other embodiments, the trenches may not extendinto the substrate 102 a, and also may not extend into buffer layer 102b, depending, for example, on the trench geometry and the lateral versusvertical growth rates of the gallium nitride.

[0024] Referring now to FIG. 2, the sidewalls 105 of the underlyinggallium nitride layer 104 are laterally grown to form a lateral galliumnitride layer 108 a in the trenches 107. Lateral growth of galliumnitride may be obtained at 1000-1100° C. and 45 Torr. The precursors TEGat 13-39 μmol/min and NH₃ at 1500 sccm may be used in combination with a3000 sccm H₂ diluent. If gallium nitride alloys are formed, additionalconventional precursors of aluminum or indium, for example, may also beused. As used herein, the term “lateral” means a direction that isorthogonal to the sidewalls 105. It will also be understood that somevertical growth on the posts 106 may also take place during the lateralgrowth from sidewalls 105. As used herein, the term “vertical” denotes adirectional parallel to the sidewalls 105.

[0025] Referring now to FIG. 3, continued growth of the lateral galliumnitride layer 108 a causes vertical growth onto the underlying galliumnitride layer 104, specifically onto the posts 106, to form a verticalgallium nitride layer 108 b. Growth conditions for vertical growth maybe maintained as was described in connection with FIG. 2. As also shownin FIG. 3, continued vertical growth into trenches 107 may take place atthe bottom of the trenches.

[0026] Referring now to FIG. 4, growth is allowed to continue until thelateral growth fronts coalesce in the trenches 107 at the interfaces 108c, to form a continuous gallium nitride semiconductor layer in thetrenches. The total growth time may be approximately 60 minutes. Asshown in FIG. 5, microelectronic devices 110 may then be formed in thelateral gallium nitride semiconductor layer 108 a. Devices may also beformed in vertical gallium nitride layer 108 b.

[0027] Accordingly, in FIG. 5, gallium nitride semiconductor structures100 according to a first embodiment of the present invention areillustrated. The gallium nitride structures 100 include the substrate102. The substrate may be sapphire or gallium nitride or otherconventional substrates. However, preferably, the substrate includes the6H—SiC(0001) substrate 102 a and the aluminum nitride buffer layer 102 bon the silicon carbide substrate 102 a. The aluminum nitride bufferlayer 102 b may be 0.1 μm thick.

[0028] The fabrication of the substrate 102 is well known to thosehaving skill in the art and need not be described further. Fabricationof silicon carbide substrates are described, for example, in U.S. Pat.No. 4,865,685 to Palmour; Re U.S. Pat. No. 34,861 to Davis et al.; U.S.Pat. No. 4,912,064 to Kong et al. and U.S. Pat. No. 4,946,547 to Palmouret al., the disclosures of which are hereby incorporated herein byreference.

[0029] The underlying gallium nitride layer 104 is also included on thebuffer layer 102 b opposite the substrate 102 a. The underlying galliumnitride layer 104 may be between about 1.0 and 2.0 μm thick, and may beformed using metalorganic vapor phase epitaxy (MOVPE). The underlyinggallium nitride layer generally has an undesired relatively high defectdensity. For example, dislocation densities of between about 10 ⁸ and 10¹⁰ cm⁻² may be present in the underlying gallium nitride layer. Thesehigh defect densities may result from mismatches in lattice parametersbetween the buffer layer 102 b and the underlying gallium nitride layer104, and/or other causes. These high defect densities may impact theperformance of microelectronic devices formed in the underlying galliumnitride layer 104.

[0030] Still continuing with the description of FIG. 5, the underlyinggallium nitride layer 104 includes the plurality of sidewalls 105 thatmay be defined by the plurality of pedestals 106 and/or the plurality oftrenches 107. As was described above, the sidewalls may be oblique andof various elongated shapes.

[0031] Continuing with the description of FIG. 5, the lateral galliumnitride layer 108 a extends from the plurality of sidewalls 105 of theunderlying gallium nitride layer 104. The lateral gallium nitride layer108 a may be formed using metalorganic vapor phase epitaxy at about1000-1100° C. and 45 Torr. Precursors of triethygallium (TEG) at 13-39μmol/min and ammonia (NH₃) at 1500 sccm may be used in combination witha 3000 sccm H₂ diluent, to form the lateral gallium nitride layer 108 a.

[0032] Still continuing with the description of FIG. 5, the galliumnitride semiconductor structure 100 also includes the vertical galliumnitride layer 108 b that extends vertically from the posts 106.

[0033] As shown in FIG. 5, the lateral gallium nitride layer 108 acoalesces at the interfaces 108 c to form a continuous lateral galliumnitride semiconductor layer 108 a in the trenches. It has been foundthat the dislocation densities in the underlying gallium nitride layer104 generally do not propagate laterally from the sidewalls 105 with thesame density as vertically from the underlying gallium nitride layer104. Thus, the lateral gallium nitride layer 108 a can have a relativelylow defect density, for example less that 10 ⁴ cm⁻². Accordingly, thelateral gallium nitride layer 108 b may form device quality galliumnitride semiconductor material. Thus, as shown in FIG. 5,microelectronic devices 110 may be formed in the lateral gallium nitridesemiconductor layer 108 a. It will also be understood that a mask neednot be used to fabricate the gallium nitride semiconductor structures100 of FIG. 5, because lateral growth is directed from the sidewalls105.

[0034] Referring now to FIGS. 6-10, second embodiments of galliumnitride semiconductor structures and fabrication methods according tothe present invention will now be described. First, gallium nitridesemiconductor structures of FIG. 4 are fabricated as was alreadydescribed with regard to FIGS. 1-4. Then, referring to FIG. 6, the posts106 are masked with a mask 206 that includes an array of openingstherein. The mask may comprise silicon dioxide at thickness of 1000 Åand may be deposited using low pressure chemical vapor deposition at410° C. Other masking materials may be used. The mask may be patternedusing standard photolithography techniques and etched in a buffered HFsolution. In one embodiment, the openings are 3 μm-wide openings thatextend in parallel at distances of between 3 and 40 μm and that areoriented along the <1{overscore (1)} 00> direction on the lateralgallium nitride layer 108 a. Prior to further processing, the structuremay be dipped in a 50% hydrochloric acid (HCl) solution to removesurface oxides. It will be understood that although the mask 206 ispreferably located above the posts 106, it can also be offset therefrom.

[0035] Referring now to FIG. 7, the lateral gallium nitridesemiconductor layer 108 a is grown through the array of openings to forma vertical gallium nitride layer 208 a in the openings. Growth ofgallium nitride may be obtained, as was described in connection withFIG. 2.

[0036] It will be understood that growth in two dimensions may be usedto form an overgrown gallium nitride semiconductor layer. Specifically,the mask 206 may be patterned to include an array of openings thatextend along two orthogonal directions such as <1{overscore (1)}00> and<1{overscore (1)}20 >. Thus, the openings can form a rectangle oforthogonal striped patterns. In this case, the ratio of the edges of therectangle is preferably proportional to the ratio of the growth rates ofthe {11{overscore (2)}0} and {1{overscore (1)}01} facets, for example,in a ratio of 1.4:1. The openings can be equitriangular with respect todirections such as <1{overscore (1)}00> and <11{overscore (2)}0>.

[0037] Referring now to FIG. 8, continued growth of the vertical galliumnitride layer 208 a causes lateral growth onto the mask 206, to form asecond lateral gallium nitride layer 208 b. Conditions for overgrowthmay be maintained as was described in connection with FIG. 7.

[0038] Referring now to FIG. 9, lateral overgrowth is allowed tocontinue until the lateral growth fronts coalesce at the secondinterfaces 208 c on the mask 206 to form a continuous overgrown galliumnitride semiconductor layer 208. The total growth time may beapproximately sixty minutes. As shown in FIG. 10, microelectronicdevices 210 may then be formed in the second lateral gallium nitridelayer 208 b. The microelectronic devices may also be formed in thevertical gallium nitride layer 208 a

[0039] Accordingly, by providing the second lateral growth layer 208 b,defects that were present in continuous gallium nitride semiconductorlayer 108 may be reduced even further, to obtain device quality galliumnitride in the gallium nitride semiconductor structure 200.

[0040] Referring now to FIGS. 11-15, third embodiments of galliumnitride semiconductor structures and fabrication methods according tothe present invention will now be described. First, gallium nitridesemiconductor structures of FIG. 4 are fabricated as was alreadydescribed in connection with FIGS. 1-4. Then, a plurality of secondsidewalls 305 are formed. The second sidewalls 305 may be formed byselective epitaxial growth of second posts 306 by etching secondtrenches 307 in the first posts 106 and/or combinations thereof. As wasalready described, the second sidewalls 305 need not be orthogonal tosubstrate 102, but rather may be oblique. The second trenches 307 neednot be directly over the first posts 106, but may be laterally offsettherefrom. The second trenches are preferably deep so that lateralgrowth preferentially occurs on the sidewalls 305 rather than on thebottom of second trenches 306.

[0041] Referring now to FIG. 12, the second sidewalls 305 of the secondposts 306 and/or the second trenches 307 are laterally grown to form asecond lateral gallium nitride layer 308 a in the second trenches 307.As was already described, lateral growth of gallium nitride may beobtained at 1000-1100° C. and 45 Torr. The precursors TEG at 13-39μmol/min and NH₃ at 1500 sccm may be used in combination with a 3000sccm H₂ diluent. If gallium nitride alloys are formed, additionalconventional precursors of aluminum or indium, for example, may also beused. It will also be understood that some vertical growth may takeplace on the second posts 306 during the lateral growth from the secondsidewalls 305.

[0042] Referring now to FIG. 13, continued growth of the second lateralgallium nitride layer 308 a causes vertical growth onto the second posts306, to form a second vertical gallium nitride layer 308 b. As alsoshown, vertical growth from the floors of the second trenches and fromthe tops of the second posts may also take place. Growth conditions forvertical growth may be maintained as was described in connection withFIG. 12.

[0043] Referring now to FIG. 14, growth is allowed to continue until thelateral growth fronts coalesce in the second trenches 307 at the secondinterfaces 308 c to form a second continuous gallium nitridesemiconductor layer 308. The total growth time may be approximatelysixty minutes. As shown in FIG. 15, microelectronic devices 310 may thenbe formed in the second continuous gallium nitride semiconductor layer308.

[0044] Accordingly, third embodiments of gallium nitride semiconductorstructures 300 according to the present invention may be formed withoutthe need to mask gallium nitride for purposes of defining lateralgrowth. Rather, lateral growth from first and second sidewalls may beused. By performing two separate lateral growths, the defect density maybe reduced considerably.

[0045] Additional discussion of methods and structures of the presentinvention will now be provided. The first and second trenches 107 and307 and the openings in the mask 206 are preferably rectangular trenchesand openings that preferably extend along the <11{overscore (2)}0>and/or <1{overscore (1)}00> directions on the underlying gallium nitridelayer 104 or the first lateral gallium nitride layer 108 a. Truncatedtriangular stripes having (1{overscore (1)}01) slant facets and a narrow(0001) top facet may be obtained for trenches and/or mask openings alongthe <11{overscore (2)}0> direction. Rectangular stripes having a (0001)top facet, (11{overscore (2)}0) vertical side faces and (1{overscore(1)}01) slant facets may be grown along the <1{overscore (1)}00>direction. For growth times up to 3 minutes, similar morphologies may beobtained regardless of orientation. The stripes develop into differentshapes if the growth is continued.

[0046] The amount of lateral growth generally exhibits a strongdependence on trench and/or mask opening orientation. The lateral growthrate of the <1{overscore (1)}00> oriented trenches and/or mask openingsis generally much faster than those along <11{overscore (2)}0>.Accordingly, it is most preferred to orient the trenches and/or maskopenings, so that they extend along the <1{overscore (1)}00> directionof the underlying gallium nitride layer 104 or the first lateral galliumnitride layer 108 a.

[0047] The different morphological development as a function of trenchand/or mask opening orientation appears to be related to the stabilityof the crystallographic planes in the gallium nitride structure.Trenches and/or mask openings oriented along <11{overscore (2)}0> mayhave wide (1{overscore (1)}00) slant facets and either a very narrow orno (0001) top facet depending on the growth conditions. This may bebecause (1{overscore (1)}01) is the most stable plane in the galliumnitride wurtzite crystal structure, and the growth rate of this plane islower than that of others. The {1{overscore (1)}01} planes of the<1{overscore (1)}00> oriented trenches and/or mask openings may be wavy,which implies the existence of more than one Miller index. It appearsthat competitive growth of selected {1{overscore (1)}01} planes occursduring the deposition which causes these planes to become unstable andwhich causes their growth rate to increase relative to that of the(1{overscore (1)}01) of trenches and/or mask openings oriented along<11{overscore (2)}0>.

[0048] The morphologies of the gallium nitride layers selectively grownfrom trenches and/or mask openings oriented along <1{overscore (1)}00>are also generally a strong function of the growth temperatures. Layersgrown at 1000° C. may possess a truncated triangular shape. Thismorphology may gradually change to a rectangular cross-section as thegrowth temperature is increased. This shape change may occur as a resultof the increase in the diffusion coefficient and therefore the flux ofthe gallium species along the (0001) top plane onto the {1101} planeswith an increase in growth temperature. This may result in a decrease inthe growth rate of the (0001) plane and an increase in that of the{1101}. This phenomenon has also been observed in the selective growthof gallium arsenide on silicon dioxide. Accordingly, temperatures of1100° C. appear to be most preferred.

[0049] The morphological development of the gallium nitride regions alsoappears to depend on the flow rate of the TEG. An increase in the supplyof TEG generally increases the growth rate in both the lateral and thevertical directions. However, the lateral/vertical growth rate ratiodecrease from 1.7 at the TEG flow rate of 13 μmol/min to 0.86 at 39μmol.min. This increased influence on growth rate along <0001> relativeto that of <11{overscore (2)}0> with TEG flow rate may be related to thetype of reactor employed, wherein the reactant gases flow vertically andperpendicular to the substrate. The considerable increase in theconcentration of the gallium species on the surface may sufficientlyimpede their diffusion to the {1{overscore (1)}01} planes such thatchemisorption and gallium nitride growth occur more readily on the(0001) plane.

[0050] Continuous 2 μm thick gallium nitride semiconductor layers may beobtained using 3 μm wide trenches and/or mask openings spaced 7 μm apartand oriented along <1{overscore (1)}00>, at 1100° C. and a TEG flow rateof 26 μmol/min. The continuous gallium nitride semiconductor layers mayinclude subsurface voids that form when two growth fronts coalesce.These voids may occur most often using lateral growth conditions whereinrectangular trenches and/or mask openings having vertical {11{overscore(2)}0} side facets developed.

[0051] The continuous gallium nitride semiconductor layers may have amicroscopically flat and pit-free surface. The surfaces of the laterallygrown gallium nitride layers may include a terrace structure having anaverage step height of 0.32 nm. This terrace structure may be related tothe laterally grown gallium nitride, because it is generally notincluded in much larger area films grown only on aluminum nitride bufferlayers. The average RMS roughness values may be similar to the valuesobtained for the underlying gallium nitride layer 104.

[0052] Threading dislocations, originating from the interface betweenthe underlying gallium nitride layer 104 and the buffer layer 102 b,appear to propagate to the top surface of the underlying gallium nitridelayer 104. The dislocation density within these regions is approximately10 ⁹ cm⁻². By contrast, threading dislocations do not appear to readilypropagate laterally. Rather, the lateral gallium nitride regions 108 aand 308 a contain only a few dislocations. These few dislocations may beformed parallel to the (0001) plane via the extension of the verticalthreading dislocations after a 90° bend in the regrown region. Thesedislocations do not appear to propagate to the top surface of theovergrown gallium nitride layer.

[0053] As described, the formation mechanism of the selectively growngallium nitride layers is lateral epitaxy. The two main stages of thismechanism are vertical growth and lateral growth. During vertical growththrough a mask, the deposited gallium nitride grows selectively withinthe mask openings more rapidly than it grows on the mask, apparently dueto the much higher sticking coefficient, s, of the gallium atoms on thegallium nitride surface (s=1) compared to on the mask (s<<1). Since theSiO₂ bond strength is 799.6 kJ/mole and much higher than that of Si—N(439 kJ/mole), Ga—N (103 kJ/mole), and Ga—O (353.6 kJ/mole), Ga or Natoms should not readily bond to the mask surface in numbers and for atime sufficient to cause gallium nitride nuclei to form. They wouldeither evaporate or diffuse along the mask surface to the opening in themask or to the vertical gallium nitride surfaces which have emerged.During lateral growth, the gallium nitride grows simultaneously bothvertically and laterally.

[0054] Surface diffusion of gallium and nitrogen on the gallium nitridemay play a role in gallium nitride selective growth. The major source ofmaterial appears to be derived from the gas phase. This may bedemonstrated by the fact that an increase in the TEG flow rate causesthe growth rate of the (0001) top facets to develop faster than the(1{overscore (1)}01) side facets and thus controls the lateral growth.

[0055] The laterally grown gallium nitride bonds to the underlying masksufficiently strongly so that it generally does not break away oncooling. However, lateral cracking within the SiO₂ mask may take placedue to thermal stresses generated on cooling. The viscosity (ρ) of theSiO₂ at 1050° C. is about 10^(15.5) poise which is one order ofmagnitude greater than the strain point (about 10^(14.5) poise) wherestress relief in a bulk amorphous material occurs within approximatelysix hours. Thus, the SiO₂ mask may provide limited compliance oncooling. As the atomic arrangement on the amorphous SiO₂ surface isquite different from that on the GaN surface, chemical bonding may occuronly when appropriate pairs of atoms are in close proximity. Extremelysmall relaxations of the silicon and oxygen and gallium and nitrogenatoms on the respective surfaces and/or within the bulk of the SiO₂ mayaccommodate the gallium nitride and cause it to bond to the oxide.Accordingly, the embodiments of FIGS. 1-5 and 11-15, which need notemploy a mask, may be particularly advantageous.

[0056] In conclusion, lateral epitaxial overgrowth may be obtained fromsidewalls of an underlying gallium nitride layer via MOVPE. The growthmay depend strongly on the sidewall orientation, growth temperature andTEG flow rate. Coalescence of overgrown gallium nitride regions to formregions with both extremely low densities of dislocations and smooth andpit-free surfaces may be achieved through 3 μm wide trenches between 7μm wide posts and extending along the <1{overscore (1)}00> direction, at1100° C. and a TEG flow rate of 26 μmol/min. The lateral overgrowth ofgallium nitride from sidewalls via MOVPE may be used to obtain lowdefect density regions for microelectronic devices, without the need touse masks.

[0057] In the drawings and specification, there have been disclosedtypical preferred embodiments of the invention and, although specificterms are employed, they are used in a generic and descriptive senseonly and not for purposes of limitation, the scope of the inventionbeing set forth in the following claims.

That which is claimed
 1. A method of fabricating a gallium nitridesemiconductor layer comprising the step of: laterally growing a sidewallof an underlying gallium nitride layer into a trench in the underlyinggallium nitride layer to thereby form a lateral gallium nitridesemiconductor layer.
 2. A method according to claim 1 wherein thelaterally growing step is followed by the step of formingmicroelectronic devices in the lateral gallium nitride semiconductorlayer.
 3. A method according to claim 1 wherein the laterally growingstep comprises the step of growing a pair of sidewalls of the underlyinggallium nitride layer into a trench in the underlying gallium nitridelayer between the pair of sidewalls until the grown pair of sidewallscoalesce in the trench.
 4. A method according to claim 1 wherein thelaterally growing step comprises the step of laterally growing thesidewall of the underlying gallium nitride layer using metalorganicvapor phase epitaxy.
 5. A method according to claim 1 wherein thelaterally growing step is preceded by the step of forming the underlyinggallium nitride layer including the sidewall on a substrate.
 6. A methodaccording to claim 5 wherein the forming step comprises the steps of:forming a buffer layer on a substrate; and forming the underlyinggallium nitride layer on the buffer layer opposite the substrate.
 7. Amethod according to claim 5 wherein the forming step comprises the stepof forming the trench in the underlying gallium nitride layer, thetrench including the sidewall.
 8. A method according to claim 5 whereinthe forming step comprises the step of forming a post on the underlyinggallium nitride layer, the post including the sidewall and defining thetrench.
 9. A method according to claim 1 wherein the underlying galliumnitride layer includes a predetermined defect density, and wherein thestep of laterally growing a sidewall of an underlying gallium nitridelayer into a trench in the underlying gallium nitride layer to therebyform a lateral gallium nitride layer comprises the steps of: laterallygrowing the sidewall of the underlying gallium nitride layer to therebyform the lateral gallium nitride layer of lower defect density than thepredetermined defect density; and vertically growing the lateral galliumnitride layer while propagating the lower defect density.
 10. A methodaccording to claim 1 wherein the growing step comprises the step ofgrowing the sidewall of the underlying gallium nitride layer usingmetalorganic vapor phase epitaxy of triethylgallium at 13-39 μmol/minand ammonia at 1500 sccm at a temperature of 1000° C.-1100° C.
 11. Amethod according to claim 7 wherein the trench forming step comprisesthe step of selectively etching the underlying gallium nitride layer toform the trench that includes the sidewall.
 12. A method according toclaim 8 wherein the post forming step comprises the step of selectivelygrowing the underlying gallium nitride layer to form the post includingthe sidewall.
 13. A gallium nitride semiconductor structure comprising:an underlying gallium nitride layer including a trench having asidewall; and a lateral gallium nitride layer that extends from thesidewall of the underlying gallium nitride layer into the trench.
 14. Astructure according to claim 13 further comprising: a vertical galliumnitride layer that extends from the lateral gallium nitride layer.
 15. Astructure according to claim 13 further comprising: a plurality ofmicroelectronic devices in the vertical gallium nitride layer.
 16. Astructure according to claim 13 further comprising a substrate, andwherein the underlying gallium nitride layer is on the substrate.
 17. Astructure according to claim 16 further comprising a buffer layerbetween the substrate and the underlying gallium nitride layer.
 18. Astructure according to claim 13 wherein the trench includes a pair ofthe sidewalls, and wherein the lateral gallium nitride layer extendsfrom the pair of sidewalls to define a continuous lateral galliumnitride.
 19. A structure according to claim 13 wherein the underlyinggallium nitride layer includes a post thereon, the post including thesidewall and defining the trench.
 20. A structure according to claim 13wherein the underlying gallium nitride layer includes a predetermineddefect density, wherein the lateral gallium nitride layer is of lowerdefect density than the predetermined defect density.
 21. A method offabricating a gallium nitride semiconductor layer comprising the stepof: laterally growing a plurality of sidewalls of an underlying galliumnitride layer into a plurality of trenches in the underlying galliumnitride layer to thereby form a lateral gallium nitride layer.
 22. Amethod according to claim 21 wherein the laterally growing step isfollowed by the steps of: masking the lateral gallium nitride layer witha mask that includes an array of openings therein; and growing thelateral gallium nitride layer through the array of openings and onto themask, to thereby form an overgrown gallium nitride semiconductor layer.23. A method according to claim 21 wherein the growing step is followedby the steps of: vertically growing the lateral gallium nitride layer;forming a plurality of second sidewalls in the vertically grown lateralgallium nitride layer to define a plurality of second trenches; andlaterally growing the plurality of second sidewalls of the verticallygrown lateral gallium nitride layer into the plurality of secondtrenches, to thereby form a second lateral gallium nitride semiconductorlayer.
 24. A method according to claim 22 wherein the laterally growingstep is followed by the step of forming microelectronic devices in theovergrown gallium nitride semiconductor layer.
 25. A method according toclaim 23 wherein the step of laterally growing the plurality of secondsidewalls is followed by the step of forming microelectronic devices inthe second lateral gallium nitride semiconductor layer.
 26. A methodaccording to claim 21 wherein the laterally growing step comprises thestep of growing the plurality of sidewalls of the underlying galliumnitride layer into the plurality of trenches in the underlying galliumnitride layer until the plurality of grown sidewalls coalesce in thetrenches.
 27. A method according to claim 22 wherein the growing stepcomprises the step of growing the lateral gallium nitride layer throughthe array of openings and onto the mask until the grown lateral galliumnitride layer coalesces on the mask to form a continuous overgrowngallium nitride semiconductor layer.
 28. A method according to claim 23wherein the step of laterally growing the plurality of second sidewallscomprises the step of laterally growing the plurality of secondsidewalls of the vertically grown lateral gallium nitride layer into theplurality of second trenches until the plurality of laterally grownsecond sidewalls coalesce in the plurality of second trenches.
 29. Amethod according to claim 21 wherein the laterally growing stepcomprises the step of laterally growing the plurality of sidewalls ofthe underlying gallium nitride layer using metalorganic vapor phaseepitaxy.
 30. A method according to claim 21 wherein the laterallygrowing step is preceded by the step of forming the underlying galliumnitride layer including the plurality of sidewalls on a substrate.
 31. Amethod according to claim 30 wherein the forming step comprises thesteps of: forming a buffer layer on a substrate; and forming theunderlying gallium nitride layer on the buffer layer opposite thesubstrate.
 32. A method according to claim 30 wherein the forming stepcomprises the step of forming the plurality of trenches in theunderlying gallium nitride layer, the plurality of trenches includingthe plurality of sidewalls.
 33. A method according to claim 30 whereinthe forming step comprises the step of forming a plurality of posts inthe underlying gallium nitride layer, the plurality of posts includingthe plurality of sidewalls and defining the plurality of trenches.
 34. Amethod according to claim 21 wherein the underlying gallium nitridelayer includes a predetermined defect density, and wherein the step oflaterally growing a plurality of sidewalls of the underlying galliumnitride layer into the plurality of trenches in the underlying galliumnitride layer to thereby form a lateral gallium nitride layer comprisesthe steps of: laterally growing the plurality of sidewalls of theunderlying gallium nitride layer into the plurality of trenches tothereby form a lateral gallium nitride semiconductor layer of lowerdefect density than the predetermined defect density; and verticallygrowing the laterally gallium nitride layer while propagating the lowerdefect density.
 35. A method according to claim 21 wherein the laterallygrowing step comprises the step of laterally growing the plurality ofsidewalls of the underlying gallium nitride layer using metalorganicvapor phase epitaxy of triethylgallium at 13-39 μmol/min and ammonia at1500 sccm at a temperature of 1000° C.-1100° C.
 36. A gallium nitridesemiconductor structure comprising: an underlying gallium nitride layerincluding a plurality of trenches have a plurality of sidewalls; and alateral gallium nitride layer that extends from the plurality ofsidewalls of the underlying gallium nitride layer into the plurality oftrenches.
 37. A structure according to claim 36 further comprising: amask including an array of openings therein on the lateral galliumnitride layer; and a vertical gallium nitride layer that extends fromthe lateral gallium nitride layer, through the openings and onto themask.
 38. A structure according to claim 36 further comprising: avertical gallium nitride layer that extends from the lateral galliumnitride layer, wherein the vertical gallium nitride layer includes aplurality of second sidewalls therein; and a second lateral galliumnitride layer that extends from the plurality of second sidewalls.
 39. Astructure according to claim 37 further comprising: a plurality ofmicroelectronic devices in the lateral gallium nitride layer.
 40. Astructure according to claim 38 further comprising: a plurality ofmicroelectronic devices in the second lateral gallium nitride layer. 41.A structure according to claim 36 further comprising a substrate, andwherein the underlying gallium nitride layer is on the substrate.
 42. Astructure according to claim 41 further comprising a buffer layerbetween the substrate and the underlying gallium nitride layer.
 43. Astructure according to claim 36 wherein the lateral gallium nitridelayer extends from the plurality of sidewalls into the plurality oftrenches to define a continuous lateral gallium nitride layer in thetrenches.
 44. A structure according to claim 36 wherein the underlyinggallium nitride layer includes a plurality of posts thereon, theplurality of posts including the plurality of sidewalls and defining theplurality of trenches.
 45. A structure according to claim 36 wherein theunderlying gallium nitride layer includes a predetermined defect densityand wherein the lateral gallium nitride layer is of lower defect densitythan the predetermined defect density.